Typically during a fabrication process of an integrated circuit, a semiconductor wafer is subjected to various processes for depositing multiple layers of dielectric and conductive materials onto the wafer. After deposition, the multiple layers are wired together or interconnected to form the integrated circuit. Typically, the “wiring” of an integrated circuit involves pattern etching of features, such as trenches and “vias,” in the dielectric material and filling the features with the conductive material.
Copper has been used as the conductive material for forming conductive contacts and interconnects because of its relatively low susceptibility to electromigration and low resistivity. However, because copper does not readily form volatile or soluble compounds, patterned etching of copper is difficult. Thus, the copper conductive contacts and interconnects are formed using a damascene process.
In accordance with a typical damascene process, the copper conductive contacts and interconnects are formed by creating a via within an insulating material. A barrier layer is deposited onto the surface of the insulating material and into the via. The barrier layer prevents contamination caused by copper diffusing through the interlayer dielectrics and may be formed of any suitable material, such as, for example, tantalum (Ta) and/or tantalum nitride (TaN). Next, a seed layer of copper is deposited over the barrier layer. Then, a copper metallization layer is electrodeposited over the seed layer to fill the via. Excess copper from the metallization layer and the seed layer and excess Ta and/or TaN from the barrier layer overlying the insulating material outside the via are then removed by a chemical mechanical planarization process.
Chemical mechanical planarization, also known as chemical mechanical polishing (referred to herein collectively as “CMP”), is a technique that has been conventionally used for the planarization of semiconductor wafers. CMP also is often used in the formation of microelectronic devices to provide a substantially smooth, planar surface suitable for subsequent fabrication processes such as photoresist coating and pattern definition. A typical CMP apparatus suitable for planarizing a semiconductor surface generally includes a wafer carrier configured to support, guide, and apply pressure to a wafer during the polishing process, a polishing compound such as a slurry to assist in the removal of material from the surface of the wafer, and a polishing surface such as a polishing pad. In addition, the polishing apparatus may include an integrated wafer cleaning system and/or an automated load/unload station to facilitate automatic processing of the wafers.
A wafer surface is generally polished by moving the surface of the wafer to be polished relative to the polishing surface in the presence of the slurry. In particular, the wafer is placed in the carrier such that the surface to be polished is placed in contact with the polishing surface, and the polishing surface and/or the wafer are moved relative to each other while slurry is supplied to the polishing surface.
Although chemical mechanical planarization processes effectively remove materials from the metallization, seed, and barrier layers, these processes may have some drawbacks. For example, mechanical polishing may inadvertently damage the metallization and/or seed layers or may leave stresses in the wafer leading to subsequent cracking and shorting between the layers. Furthermore, the CMP process may result in sheering or crushing of fragile layers, such as layers made of low dielectric constant materials. In circumstances in which the barrier layer comprises Ta and/or Ta/N, this drawback may become even more pronounced. Generally, Ta and/or Ta/N are relatively harder to remove from a semiconductor wafer than the materials of a metallization or a seed layer. Thus, a relatively high force may need to be exerted by the polishing surface against the barrier layer, which may undesirably leave stresses in the underlying layer made of low dielectric constant material. The CMP process, further, due to its dependence on high pressures, oxidizing agents and pad bending, also may tend to cause dishing in the center of wide metal features, such as trenches and vias, oxide erosion between metal features, and dielectric oxide loss.
Accordingly, it is desirable to have a method and compositions for use in the method that remove material from the barrier layer, metallization layer, and seed layer without damaging the metallization and/or seed layer and/or the dielectric layer. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.